Free Architecture & memory lessons
Instructions and data share an organized machine
The instruction set architecture defines visible instructions, registers, data types, addressing, exceptions, and memory behaviour. A microarchitecture implements that contract with datapaths, control, pipelines, and caches. Different processors can run the same binary while arranging the internal work very differently.
A load encodes an operation, destination register, and address calculation. Control decodes it; the datapath computes the address; the memory system locates the bytes; the result is extended or interpreted as specified and written to the destination. Exceptions must leave an architecturally defined state.
Locality turns a speed gap into a workable illusion
Registers are tiny and immediate; caches hold recently useful blocks; DRAM supplies larger working memory; storage provides capacity and persistence. The hierarchy works because programs often reuse recent data and nearby addresses. A miss pays the cost of moving a whole block from a farther layer.
If a cache hit costs 1 ns and one access in 100 misses at a 100 ns extra penalty, misses add about 1 ns on average—roughly doubling the effective time. A small miss-rate change matters because the distant access is so expensive.
The processor is not the whole computer
Devices expose control and status through registers, often memory-mapped. Polling repeatedly asks for progress; interrupts let a device request CPU attention; direct memory access moves blocks between a device and memory with limited CPU involvement. Drivers translate operating-system requests into device-specific protocols.
When an enabled event arrives, the processor preserves enough execution context, identifies an appropriate handler, and transfers control. The handler acknowledges or services the source, schedules deferred work if needed, and eventually restores the interrupted context. Priority and masking keep urgent work bounded.
Reason with bottlenecks, parallelism, and measurement
Instruction count, cycles per instruction, and clock period offer one decomposition, but memory stalls, I/O waits, contention, and parallel work complicate it. Amdahl’s law states that improving one fraction of execution limits total speedup according to how much time that fraction originally consumed.
Wall time says the user-visible outcome. Hardware counters can show instructions, cycles, branches, and cache misses; system tools expose I/O and scheduling. Compare a hypothesis with several measurements: high last-level misses plus stalled cycles supports a memory-bound diagnosis more than instruction count alone.