FREE LESSON · Architecture & memory · 3 OF 4
Interrupts, Polling and DMA Explained
Devices, interrupts, and DMA — The processor is not the whole computer
I/O is communication with independently timed devices.
Devices expose control and status through registers, often memory-mapped. Polling repeatedly asks for progress; interrupts let a device request CPU attention; direct memory access moves blocks between a device and memory with limited CPU involvement. Drivers translate operating-system requests into device-specific protocols.
The right mechanism depends on event rate, latency target, transfer size, and CPU cost.
An interrupt is a controlled change of flow
When an enabled event arrives, the processor preserves enough execution context, identifies an appropriate handler, and transfers control. The handler acknowledges or services the source, schedules deferred work if needed, and eventually restores the interrupted context. Priority and masking keep urgent work bounded.
Interrupts improve responsiveness but excessive interrupts can consume the machine they are meant to help.