The question this layer answers
How do materials become reliable switches?
Controlling physical state. This layer connects Transistors, CMOS, Clocks, Fabrication to the rest of the computing stack.
From a controlled current to a logical operation
A MOS transistor uses the electric field from its insulated gate to control a conducting path. The digital abstraction calls that path “on” or “off.” The physical device has resistance, capacitance, leakage, and a transition region. The abstraction is useful because it hides detail, but those omitted details determine speed and energy.
A CMOS inverter connects a pMOS pull-up to the supply and an nMOS pull-down to ground. Their gates share the input and their drains share the output. At a low input, the pull-up conducts and the pull-down is off; the output charges toward the supply. At a high input, the pull-up is off and the pull-down conducts; the output discharges toward ground.
| Stable input | Pull-up | Pull-down | Stable output |
|---|
| Low | On | Off | High |
| High | Off | On | Low |
This table describes settled endpoints. During a transition both devices may conduct partially. Real devices also leak at the endpoints. “Low static power” therefore means neither literally zero power nor zero energy to switch.
Why moving charge takes time
The output wire and the gates it drives form an effective load capacitance C. Moving its voltage by ΔV requires charge Q = CΔV. Current is charge per unit time, so limited current means nonzero delay. Adding more receiving gates increases the load: the same logical NOT operation can become slower without changing its truth table.
In a simple resistive approximation, a characteristic charging time is proportional to RC. This is a model for reasoning, not a substitute for a device's timing characterization. Manufacturing variation and temperature also alter the currents and delays.
Calculate switching power carefully
A common estimate is Pdynamic ≈ α C V² f, where α counts average charging activity per clock cycle under the chosen convention, C is switched capacitance, V is supply voltage, and f is clock frequency. For α = 0.2, C = 10 pF, V = 1 V, and f = 100 MHz, the estimate is 0.2 mW. Doubling frequency doubles this term if everything else stays fixed; reducing V to 0.8 V scales it by 0.64.
Those qualifications matter. Lower voltage can slow switching and require a lower clock. Static leakage and transition current are not included in this simple estimate. A workload changes α, so transistor count alone does not determine energy use.
Before moving on: explain why an inverter driving ten inputs may need a different timing budget than one driving a single input. Then draw the conducting path for each stable input in the lab. You should be able to move between three views: a truth table, a current path, and a charging process. None replaces the others.
Free Semiconductors & electronics lessons
Why semiconductors make switching possible
Semiconductor behaviour can be shaped through material composition, geometry, and electric fields. In a MOSFET, voltage at an insulated gate changes whether a conductive channel forms between source and drain. The gate therefore controls current while ideally drawing little steady current itself.
A real transistor needs time to charge and discharge capacitances. It leaks when nominally off, has resistance when on, and changes behaviour with temperature and manufacturing variation. Logic design hides much of this until speed, power, or reliability reaches a limit.
Complementary devices restore a bit
A CMOS inverter pairs a pull-up network with a pull-down network. A low input turns on the path toward the supply and turns off the path to ground, producing high; a high input does the reverse. Around the switching threshold both may partly conduct, but stable endpoints restore strong logic levels.
To change the output, the circuit must move charge onto or off its effective capacitance. Roughly, dynamic energy grows with capacitance and the square of supply voltage, and power also grows with switching frequency. More activity, larger loads, or higher voltage therefore costs heat.
Why billions of switches are a systems problem
Fabrication produces variation in dimensions and electrical properties. Voltage and temperature change delay and leakage during operation. Designers close timing against defined corners and paths, distribute clocks, constrain power density, and use testing and redundancy to manage defects.
Between two state elements, combinational logic and wires consume time. The slowest relevant path must settle before the next capture edge, with margins for uncertainty. Shortening unrelated paths does not raise the safe clock; the critical path must change, or the work must be pipelined across more cycles.
Reason across logic, timing, power, and yield
Scaling can increase density and reduce some capacitances, enabling more computation. But leakage, interconnect delay, variability, power delivery, heat removal, and fabrication cost can become dominant. Progress therefore comes from architecture, packaging, specialized accelerators, and software as well as transistor geometry.
Wrong outputs at every speed suggest a logical or connectivity defect. Failures only at high frequency suggest delay. Failures only when hot implicate thermal or leakage-sensitive margin. Failures on a subset of chips suggest process variation or defects. Controlled changes turn symptoms into discriminating evidence.
Use an RC approximation to calculate timing and dynamic power.
Separate defect yield, timing yield, and failures over time.
Practice lab: Build an inverter from two switches
About 25 minutes. Know what low and high mean from Signals. Treat each transistor as an ideal controlled switch for this exercise.
Connect a PMOS between the supply and output, and an NMOS between output and ground. Both gates share input A. Use ideal switches first. For the energy estimate only, assume dynamic power P = α C V² f, with activity α, capacitance C, supply V, and switching frequency f.
- Make a table for A = 0 and A = 1: which switch conducts, and what is the output?
- Explain why connecting both switches as NMOS would not implement the same truth table in this ideal model.
- Calculate the dynamic-power ratio when V is multiplied by 0.8 and f by 1.25, with α and C unchanged. State what this model leaves out.
Hint
For each row, trace a conducting path from the output to either supply or ground. Square the voltage ratio before multiplying by frequency.
Worked solution
At A = 0, PMOS conducts and NMOS is off, so the output is high. At A = 1, PMOS is off and NMOS conducts, so the output is low. With two ideal NMOS switches, A = 0 leaves the output floating and A = 1 connects supply to ground: neither is a valid inverter contract. The dynamic-power ratio is 0.8² × 1.25 = 0.80, a 20% reduction under the stated assumptions. Real devices have leakage, resistance, capacitance, and transition current. Lower supply can also increase delay; the formula does not prove that the higher clock rate is achievable.
- Give both truth-table rows and the conducting path.
- Distinguish ideal switching from physical transition behaviour.
- Keep the power calculation conditional on the timing assumption.
Change one assumption
Add capacitance at the output. Explain why the logical truth table can stay the same while the fastest reliable clock becomes slower.
Quantify a switching design
Treat circuit equations as stated approximations. Calculate timing, energy, and yield, then identify the physical effects that the model omits.
1. Circuit reasoning · allow 30 minutes
Trace a CMOS inverter through valid and intermediate inputs
Use an ideal CMOS inverter with a p-channel pull-up to VDD and n-channel pull-down to ground. For input 0 and inputVDD, state which device conducts, the output, and whether there is an ideal steady conduction path between rails.
Explain what the ideal switch model omits during an input transition and while charging a load capacitor. A student concludes that CMOS therefore uses no energy. Refute that claim by distinguishing static leakage, short-circuit current during a transition, and capacitive switching. State why two outputs should not be connected together merely because both are digital.
Get a starting hint
An output node stores charge. “No ideal steady rail-to-rail path” is narrower than “no energy consumption.”
Compare your reasoning with the worked solution
At input 0 the p-channel device conducts and the n-channel device is off, pulling the output high. At inputVDD the p-channel device is off and the n-channel device conducts, pulling the output low. In those ideal settled cases there is no conducting path through both devices from supply to ground.
Real devices leak even in a nominal off state. During a finite input transition both devices can partly conduct, creating short-circuit current. Charging and discharging the output capacitance also requires energy even if that overlap were eliminated. The binary switch model does not determine analog voltage-transfer curves, gain, transition duration, or noise margins; those require device behavior and loading assumptions.
Connecting two ordinary push-pull outputs can produce contention when one drives high and the other low, forming a low-resistance path between rails. A shared bus needs an explicit electrical protocol, such as controlled tri-state drivers or an appropriately designed open-drain arrangement. Agreement about bit meanings is not an electrical permission to tie drivers together.
Check your reasoning
- Trace both device states and the output.
- Name three distinct energy mechanisms.
- Explain contention through a physical current path.
2. Derive and calculate · allow 35 minutes
Find a timing budget from an exponential response
A first-order model charges capacitance C through resistance R from 0 toward VDD: V(t)=VDD(1−exp(−t/RC)). Let R=2 kΩ,C=20 fF,VDD=1 V. Derive the time to reach 0.7 V and calculate it.
A receiver samples at 60 ps. Find the largest capacitance that reaches the threshold by then under this model. Recalculate after resistance rises by 25%. Explain why treating this result as an exact transistor timing specification would exceed the model.
Get a starting hint
Solve the threshold equation with a logarithm. Keep femtofarads and picoseconds explicit.
Compare your reasoning with the worked solution
Setting V/VDD=0.7 gives exp(−t/RC)=0.3, hence t=−RC ln(0.3). RC=2000×20×10^−15=40 ps, so t≈48.159 ps. For a 60 ps deadline, C≤60×10^−12/[2000×(−ln 0.3)]≈24.917 fF.
With resistance 2500 Ω, the original 20 fF load reaches threshold in 60.199 ps, slightly missing the deadline. The maximum permissible capacitance becomes about 19.933 fF. This small change shows why checking a rounded “about 60” value can hide a violation.
The model assumes fixed resistance, a single lumped capacitance, an ideal supply step, and a fixed threshold. Actual transistor current depends on terminal voltages; interconnect has distributed effects; process, temperature, supply variation, and receiver setup time add constraints. The calculation is a useful bound within a declared approximation, not a replacement for characterized timing and margins.
Check your reasoning
- Derive the logarithm before substituting values.
- Convert units correctly and retain enough precision at the boundary.
- Separate model assumptions from physical characterization.
3. Energy accounting · allow 35 minutes
Distinguish stored energy from supply energy
An ideal voltage source charges an initially empty capacitor C=10 pF to V=1.2 V through a resistor. Calculate final stored energy, energy supplied by the source, and energy dissipated in the resistor. Then discharge to ground and account for the full cycle.
An aggregate switched capacitance of 10 pF undergoes 200 million complete charge-discharge cycles per second. Calculate dynamic power. Recalculate at 0.9 V and 300 million cycles per second. Explain what this comparison says and does not say about an actual processor's total power or performance.
Get a starting hint
Integrate supply voltage times delivered charge for source energy. A full cycle starts and ends with zero stored capacitor energy.
Compare your reasoning with the worked solution
The capacitor stores CV²/2=7.2 pJ. The source delivers chargeCV at fixed voltageV, so it supplies CV²=14.4 pJ. The resistor dissipates the remaining 7.2 pJ during charging. Discharge dissipates the stored 7.2 pJ, making total cycle dissipation 14.4 pJ.
At 200 million full cycles per second, dynamic power is 14.4×10^−12×200×10^6=2.88 mW. At 0.9 V and 300 million cycles per second it is 10×10^−12×0.9²×300×10^6=2.43 mW, or 84.375% of the original. Lower voltage more than offsets the increased cycle rate in this specified capacitive model.
A processor also has leakage, short-circuit current, regulator losses, and activity that varies across components. Lower voltage can increase delay and limit safe frequency. The calculation does not establish that the proposed operating point is physically achievable or that application throughput increases in proportion to the switching rate.
Check your reasoning
- Account separately for charge and discharge.
- Define the activity rate as full cycles so no factor-of-two ambiguity remains.
- Avoid turning a dynamic-power calculation into a total-system claim.
4. Probability model and sensitivity · allow 40 minutes
Expose the assumption behind a yield estimate
A toy die-yield model assumes independent random defects with Poisson mean D·A, where D is defects per cm² and A is die area in cm². A die works only if it has zero defects. Derive Y=exp(−DA). For D=0.2 and A=1.5, calculate yield.
Ignoring wafer-edge loss, a wafer supplies 600 cm² of usable area and costs 6000 units. Estimate good dies and wafer cost per good die for A=1.5 and A=0.75. List two ways clustering or defect tolerance would invalidate the simple calculation. Explain why an expected good-die count is not a guaranteed production count.
Get a starting hint
Use the Poisson zero-event probability. Compute gross die count before applying yield.
Compare your reasoning with the worked solution
For N~Poisson(DA), P(N=0)=exp(−DA)(DA)^0/0!=exp(−DA). With A=1.5, Y=exp(−0.3)≈0.740818. Gross dies are 600/1.5=400; expected good dies≈296.327; wafer cost per expected good die≈20.2479.
At A=0.75, Y=exp(−0.15)≈0.860708. Gross dies are 800; expected good dies≈688.566; the corresponding cost is≈8.71376. This comparison holds wafer cost and all excluded costs fixed. It says nothing about whether a smaller die delivers the same function. Packaging, testing, edge loss, systematic defects, and parametric failures can change the economics.
Spatially clustered defects violate a homogeneous independent-defect model. Spare memory rows or error-tolerant structures can let a die work despite some defects, violating the zero-defect success rule. Expected counts average across the assumed random process; one wafer can differ, and even a correct expectation does not establish a production confidence bound.
Check your reasoning
- Derive yield from the declared probability distribution.
- Separate gross dies, yield, and cost per good die.
- Name assumptions that change the success event or the defect distribution.
Study the underlying methods
Section project: Model CMOS switching, delay, and energy
4 to 6 hours. Build a small switch-and-RC simulator for a CMOS inverter and a two-input NAND gate. Treat an on transistor as a resistor R, an off transistor as an open circuit, and the output load as a capacitor C. A p-channel switch conducts for logic zero and an n-channel switch for logic one. Use ideal rail voltages and instantaneous input changes; this intentionally omits transistor threshold curves, leakage, and short-circuit current during transitions. Inputs are a gate choice, R, C, supply voltage, and a timed sequence of binary input vectors. Outputs are the static logic table, equivalent pull-up or pull-down resistance, and sampled output voltage over time. For each constant-input interval, use the first-order solution V(t)=Vtarget+(Vstart-Vtarget)*exp(-t/(Req*C)). Explain how series and parallel conducting paths change Req. Include an energy ledger for one complete capacitor charge and discharge, distinguishing energy drawn from the supply, energy stored, and energy dissipated. All computation can use the Python standard library, with CSV or SVG traces. Label every result as a prediction of the simplified model. Include a units table and at least one dimensional check. Plot rising and falling transitions separately, since the active network can have a different effective resistance even when both transitions implement the same gate.
Milestones
- Draw the inverter and NAND pull-up and pull-down networks and derive their truth tables.
- Compute equivalent resistance for each active path and implement the piecewise RC transient.
- Sweep load capacitance and compare the predicted half-voltage delay.
- Account for supply, capacitor, and resistor energy over a charge-discharge cycle.
Acceptance criteria
- The inverter outputs NOT A and the NAND outputs zero only for inputs 11 in every static input case.
- NAND pull-down resistance is 2R when both n-channel switches conduct; its pull-up resistance is R/2 when both p-channel switches conduct.
- A zero-to-rail transition reaches half the supply at ln(2)*Req*C within the stated sampling tolerance.
- Doubling C doubles the analytically calculated half-voltage delay while leaving the static truth table unchanged.
- A full charge from zero draws C*V^2 from the ideal supply, stores C*V^2/2, and a complete charge-discharge cycle dissipates C*V^2.
Compare two implementations of a compound Boolean function under the same load and explain the gap between logical equivalence and this model’s delay predictions.
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