FREE LESSON · Machine code & execution · 4 OF 4
CPU Pipelines, Hazards and Branch Prediction
Execution mastery: overlap without lying — Pipelines, hazards, prediction, and precise state
A pipeline overlaps work while preserving a sequential contract.
Fetch, decode, execute, memory, and retirement can operate on different instructions simultaneously. Data hazards arise from dependencies; control hazards arise before a branch outcome is known; structural hazards compete for hardware. Forwarding, stalling, prediction, and speculation recover throughput while retirement preserves defined order and exceptions.
Speculation may do work early; it must not make an unapproved result architecturally real.
A mispredicted branch wastes work, not correctness
The processor predicts a path and executes ahead. If the guess is wrong, younger speculative instructions are discarded and fetching restarts at the correct target. The architectural state must look as if only the correct path executed, though microarchitectural traces can still matter for timing and security.
“Not committed” does not mean “left no physical evidence”—a critical lesson from side-channel attacks.