A clock edge has a timing neighborhood

Prerequisites: Flip-flops, combinational delay, and clock periods.

Learning objectives

• Compute setup and hold inequalities with explicit assumptions.
• Distinguish metastability risk from a Boolean logic error.
• Choose a synchronization strategy appropriate to the signal.

Two separate timing constraints

A flip-flop samples its data input near a clock edge. Setup time requires the input to settle before that edge. Hold time requires it to remain stable afterward. These intervals describe analog requirements of the storage element, even though the system specification uses bits.

For two flip-flops driven by an ideal common clock, a setup constraint is Tclock >= tCQ,max + tlogic,max + tsetup. The source cannot produce its new output until its clock-to-Q delay has elapsed. The combinational path then needs time to propagate, and the destination requires its setup interval before the next edge.

Suppose the maximum clock-to-Q delay is 80 ps, maximum logic delay is 600 ps, and setup time is 70 ps. Ignoring skew and uncertainty, the period must be at least 750 ps, corresponding to about 1.33 GHz. A real timing budget also reserves margin for clock uncertainty and variation rather than treating nominal numbers as guarantees.

Hold uses the fastest path, not the slowest path. With zero skew, tCQ,min + tlogic,min >= thold. If these values are 30 ps, 20 ps, and 65 ps, the path fails hold by 15 ps. Slowing the clock does not repair this same-edge race. Adding appropriately characterized delay to the data path can help, but must not break setup.

An asynchronous input cannot promise alignment

An external button, another clock domain, or an independently timed device may change inside the sampling window. The receiving flip-flop may enter metastability: its internal analog state takes unusually long to settle to a valid logic level. There is no finite waiting time that makes the mathematical probability exactly zero.

A common single-bit synchronizer uses two flip-flops in the receiving clock domain. The first samples the asynchronous input; the second allows additional settling time before the signal reaches ordinary logic. Failure probability depends on device properties, settling time, and event rates. Adding a stage changes latency and can improve reliability, but does not transform an arbitrary bus into an atomic message.

Preserve the information, not merely each wire

Synchronizing the bits of a changing binary counter independently can yield a combination that never existed at the source. A short pulse can fall entirely between receiving edges and disappear. For a control event, use a handshake or a carefully designed toggle protocol. For streaming data across clocks, use an asynchronous FIFO with a proven control scheme. Reset release also deserves a clock-domain policy. The correct circuit follows from the information contract: a stable level, one event, or a multi-bit transfer each requires different reasoning.

Primary reading

• Sequential Logic (MIT OpenCourseWare, Computation Structures).

Practice problem

For a zero-skew path, use clock-to-Q maximum 90 ps, logic maximum 710 ps, and setup 100 ps. Find the minimum period. The minimum delays are 25 ps and 15 ps, with hold 60 ps. Determine the hold shortfall and explain whether reducing clock frequency helps. Finally, explain why two independent synchronizers are insufficient for a two-bit counter.

Worked solution

The setup bound is 90+710+100=900 ps, before additional margin. Its reciprocal is approximately 1.11 GHz. The earliest destination input change arrives after 25+15=40 ps, but the destination requires 60 ps of hold, so there is a 20 ps shortfall. Increasing the time to the next clock edge leaves this same-edge relationship unchanged. A deliberate data-path delay or another physical timing correction is needed. For a counter transition from binary 01 to 10, independently synchronized bits may settle in different receiving cycles. The destination could observe 00 or 11 even though neither was the intended count. Atomic transfer requires a protocol or a representation and sampling method designed for crossing domains.

Check your understanding

Which change directly addresses a zero-skew hold violation?

• Increase the clock period only.
• Reduce the maximum logic delay only.
• Increase the minimum data-path delay while rechecking setup.
• Remove the destination flip-flop’s power.

Explanation

Hold constrains the earliest same-edge arrival; adding minimum delay can repair it.

What does a two-flip-flop synchronizer provide for a stable single-bit input?

• A mathematical guarantee that metastability never occurs.
• More settling time before ordinary logic consumes the sampled value.
• Atomic transfer of any number of related bits.
• Guaranteed capture of every arbitrarily short pulse.

Explanation

It reduces propagation of metastability risk with added latency, subject to its timing assumptions.

Primary reading

• Sequential Logic: MIT OpenCourseWare, Computation Structures

Open the study and save your work →