# Lisa Su

> 1969– · Engineer, CEO of AMD
>
> **Recorded contribution:** AMD CEO; Zen architecture revival; RDNA GPUs; chiplet strategy

## How to use this dossier

Read for a causal chain, not a hero story: inherited problem → contribution → mechanism → downstream capability → limit. Then close the page and complete the reconstruction exercise from memory.

## 1. Historical orientation

Lisa Su became AMD chief executive in 2014 after engineering and leadership roles at IBM, Freescale, and AMD. Under her leadership AMD refocused roadmaps, returned to competitive high-performance processors through the Zen family, expanded graphics and data-center products, and used chiplet-based system integration. This profile belongs to computing history because institutional choices changed how technology was financed, produced, distributed, governed, or made available to complementors. The chronology is used causally: it connects the inherited constraint to an implementable mechanism and then to later reuse, instead of treating fame, job title, or eventual market success as the explanation.

## 2. The problem inherited

AMD faced weak products, limited resources, and competition from much larger firms while advanced monolithic chips became expensive and harder to manufacture at high yield. A technical possibility does not scale itself. Organizations must align capital, labor, supply, standards, distribution, maintenance, and decision rights while absorbing risk over time.

## 3. The central contribution

AMD coordinated architecture, modular chiplets, external leading-edge fabrication, packaging, memory and I/O dies, software, and multi-generation roadmaps so reusable components could serve client and server markets. The central mechanism is therefore an institutional and technical system: a product or platform boundary, an operating model, and the incentives surrounding it.

## 4. Reconstruct the mechanism

1. Select workloads and commit to a multi-generation core architecture rather than unrelated short-term products. Name the scarce technical or distribution resource and the actors who initially controlled it.
2. Partition compute and I/O into dies whose interfaces, latency, bandwidth, and manufacturing nodes fit their functions. Trace the product, contract, standard, or platform rule that coordinated those actors.
3. Source fabrication and packaging capacity while verifying the assembled system as one processor. Follow revenue, data, switching cost, operational risk, and decision authority through one real transaction.
4. Measure performance, yield, power, cost, software support, supply risk, and roadmap delivery—not leadership narrative alone. Remove a complementor, subsidy, channel, standard, or leadership decision and predict whether the system still scales.

## 5. What changed downstream

- Zen restored AMD as a major processor competitor; chiplet deployment helped normalize modular high-performance packages across the semiconductor industry.
- The result altered which technical projects could survive long enough to become infrastructure and where power accumulated around their interfaces.
- The transferable first-principles lesson is to separate the artifact named in “AMD CEO; Zen architecture revival; RDNA GPUs; chiplet strategy” from the mechanism, surrounding institution, and evidence that allowed later systems to depend on it.

## 6. Attribution, limits, and uncertainty

- Su is a strategic and technical executive, not the architect of Zen or sole originator of chiplets. Jim Keller, Mark Papermaster, architecture and verification teams, TSMC and suppliers, customers, and prior multichip work all matter. Market position and current product claims are volatile.
- Founder and executive narratives compress the work of engineering teams, predecessors, suppliers, public institutions, competitors, and users.
- The subject is living or the registry has no death year; current titles and institutional affiliations are treated as dated snapshots verified on 2026-08-09, not permanent identity claims.

## 7. Reconstruction lab

Design a 32-core processor as one monolithic die and as four compute chiplets plus I/O die. Estimate yield, area, interconnect bandwidth, latency, and validation trade-offs. Draw both the technical stack and the institutional stack, then defend a counterfactual with sources rather than personality.

## 8. Evidence trail

- [Lisa Su biography](https://www.amd.com/en/corporate/leadership/lisa-su.html) — AMD
- [Lisa Su](https://en.wikipedia.org/wiki/Lisa_Su) — Wikipedia contributors · overview and bibliography
- [Lisa Su structured identity record](https://www.wikidata.org/wiki/Q18207172) — Wikidata contributors · CC0

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*Research checked 2026-08-09. Dates, roles, and claims about living people are historical snapshots. Linked sources remain the authority; this dossier is original instructional synthesis.*